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Workshop on Mixed-Signal design and digital-on-top implementation in 28nm

Upcoming event

  7th 28 nm Mixed-Signal Design Workshop

  17-21 November 2025

  In presence at CERN

  800 CHF

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Workshop description

5-day Analog, Digital and Mixed-Signal design workshop in TSMC 28 nm.

Workshop program

  • MODULE 1: Introduction to 28 nm technology

    • Technology Overview
    • Overview of the 28nm common design platform
    • Total Ionizing Dose response of the 28nm technology
    • Guidelines for designing in 28nm - analog
    • Guidelines for designing in 28nm - digital
    • Single event effects hardening in digital design

  • MODULE 2: Analog design best practices for 28nm

    • Analog simulation with Cadence Explorer and Assembler
    • Analog Backend – layout best practices in 28nm
    • DRC, LVS and Extraction

  • MODULE 3: Preparing an analog IPs for digital-on-top design

    • Mixed-signal simulation analog-on-top
    • Mixed-signal simulation digital-on-top (in Xcelium)
    • IP block characterization: abstract view generation
    • IP block characterization: Timing models (.lib files)

  • MODULE 4: Digital physical design in 28nm

    • Digital-on-top flow introduction
    • Timing constraints
    • Radiation-tolerant techniques for SEE protection
    • Synthesis
    • Logic Equivalence Checking
    • Placement and clock-tree synthesis
    • Routing and optimization
    • Timing analysis
    • Gate-level Simulation

  • MODULE 5: Hierarchical digital-on-top design and signoff

    • Top-levelconstraints and synthesis
    • Top-level floorplan and power planning
    • Design partitioning
    • Hierarchical implementation
    • Sign-off power analysis in Voltus
    • Sign-off timing analysis
    • Sign-off DRC and LVS

Past events

Check our history of Workshops and their agenda. Already 90+ designers have taken part!