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Workshop on Mixed-Signal design and digital-on-top implementation in 28nm

Upcoming event

  7th 28 nm Mixed-Signal Design Workshop

  17-21 November 2025

  In presence at CERN

  800 CHF

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Workshop description

5-day Analog, Digital and Mixed-Signal design workshop in TSMC 28 nm.

Workshop program

  • MODULE 1: Introduction to the 28 nm technology

    • Technology overview
    • Overview of the 28 nm Common Design Platform
    • Guidelines for designing in 28 nm
    • Total Ionizing Dose response of the 28 nm technology
    • Single event effects in 28 nm

  • MODULE 2: Analog and mixed-signal simulation

    • Analog simulation with Cadence ADE Explorer and Assembler
    • Mixed-signal simulation analog-on-top
    • Mixed-signal simulation digital-on-top (in Xcelium)

  • MODULE 3: Analog design best practices

    • Analog backend: layout best practices in 28 nm
    • DRC, LVS and Extraction

  • MODULE 4: Integrating an analog IP in a digital-on-top design

    • IP block characterization: abstract view generation
    • IP block characterization: timing models (Liberty files)

  • MODULE 5: Digital design in 28nm

    • Digital-on-top flow introduction
    • Timing constraints
    • Radiation tolerance techniques for SEE protection
    • Synthesis
    • Logic Equivalence Checking
    • Placement and clock-tree synthesis
    • Routing and optimization
    • Signoff power analysis in Voltus
    • Signoff timing analysis in Tempus
    • Top-level constraints and synthesis
    • Top-level floorplan and power planning
    • Design partitioning
    • Hierarchical implementation
    • Top-level signoff power analysis
    • Top-level signoff timing analysis
    • Sign-off DRC and LVS
    • Gate-level simulation

Past events

Check our history of Workshops and their agenda. Already 90+ designers have taken part!