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Verification with UVM for HEP Workshop

Upcoming event

3rd Verification with UVM for HEP Workshop

TBA

On-site at CERN

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Workshop description

4-day UVM verification introduction and HEP-specific topics.

Workshop program

  • MODULE 1 (Days 1 to 3) - SystemVerilog accelerated verification using UVM - Cadence

    • Introduction to UVM Methodology
    • Data Modelling
    • UVM Simulation Phases
    • Test and Testbench Classes
    • Creating an Interface UVC
    • Configuration
    • Type Overrides and the Factory
    • Sequences
    • Connecting to a DUT
    • Multiple UVCs
    • Multichannel (Virtual) Sequencers
    • Building a Scoreboard
    • Transaction Level Modelling (TLM)
    • Register Modelling in UVM

  • MODULE 2 (Day 4) - Verification best practices for HEP - CERN CHIPS Service

    • Verification lifecycle
    • CHIPS Verification IPs (VIP)
    • Simulations and regressions
    • Fundamentals of SEE verification
    • Introduction to the see_uvc VIP
    • SEE simulations and fault campaigns

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