Workshop on Verification with UVM for High Energy Physics

Upcoming event

  6th Verification with UVM for HEP Workshop

  Summer 2025 TBA

  CERN Training Center

  800 CHF/EUR

Registrations are currently closed. You can join the waiting list for the next event.
The next session will be in person at the CERN training center.

Go to the event page   Enter the waiting list

Workshop description

4-day UVM verification introduction and HEP-specific topics.

Workshop program

• MODULE 1 (Days 1 to 3) - SystemVerilog accelerated verification using UVM - Cadence

  • Introduction to UVM Methodology
  • Data Modelling
  • UVM Simulation Phases
  • Test and Testbench Classes
  • Creating an Interface UVC
  • Configuration
  • Type Overrides and the Factory
  • Sequences
  • Connecting to a DUT
  • Multiple UVCs
  • Multichannel (Virtual) Sequencers
  • Building a Scoreboard
  • Transaction Level Modelling (TLM)
  • Register Modelling in UVM

• MODULE 2 (Day 4) - Verification best practices for HEP - CERN CHIPS Service

  • Verification lifecycle
  • CHIPS Verification IPs (VIP)
  • Simulations and regressions
  • Fundamentals of SEE verification
  • Introduction to the see_uvc VIP
  • SEE simulations and fault campaigns

Past events

• 5th Verification with UVM for HEP Workshop (2024 November)
• 4rd Verification with UVM for HEP Workshop (2024 March)
• 3rd SystemVerilog/UVM Verification workshop (2022 January)
• 2nd SystemVerilog/UVM Verification workshop (2021 January)
• 1st SystemVerilog/UVM Verification workshop (2020 November)

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