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CERN ASIC Support and Foundry Services
Home
Foundry services
Foundry services
Technology documents & guidelines
Technology documents & guidelines
T-28nm
T-28nm
Technical documents and design manuals
CERN Designer's guidelines
PDK access and installation
Radiation tolerance guidelines
DRC and Extraction decks
Reliability rules
T-65nm
T-65nm
Technical documents and design manuals
PDK access and installation
Radiation tolerance guidelines
DRC and Extraction decks
Total-Ionising-dose device models and libraries
T-130nm
T-130nm
Technical documents and design manuals
PDK access and installation
DRC and Extraction decks
Radiation tolerance guidelines
G-130nm
IP blocks
IP blocks
Soft IP blocks
Verification IP
Verification IP
Pin UVC
Clock generator UVC
I2C UVC
Wishbone UVC
Hit injection UVC
SEE injection UVC
T-28nm full-custom IPs
T-28nm full-custom IPs
RadTol ESD protections
RadTol CMOS IO pads
TSMC electrical fuse
Bandgap voltage reference
SRAM
SLVS TX and RX
16-bit Σ∆ ADC
8-bit rail-to-rail DAC
12-bit Σ∆ DAC
Fast rail-to-rail opamp
Low-power rail-to-rail opamp
Digital PLL
TID monitoring circuit
T-65nm full-custom IPs
T-65nm full-custom IPs
RadTol ESD protections
RadTol CMOS IO pads
TSMC electrical fuse
Bandgap Voltage Reference
RadTol SRAM
High Density SRAM
T-130nm full-custom IPs
T-130nm full-custom IPs
RadTol ESD protections
RadTol CMOS IO pads
TSMC electrical fuse
Bandgap Reference Voltage with eFuse
RadTol SRAM
G-130nm full-custom IPs
Design flows
Design flows
TSMC 28 - Flowkit
TSMC 65 - Flowkit
TSMC 65 - Stylus UI
TSMC 130 - Flowkit
TPSCO 65 - Flowkit
GF 130 - Stylus UI
Training
Training
28nm Mixed-Signal design and digital-on-top implementation Workshop
Verification with UVM for HEP Workshop
NDA & Export control
NDA & Export control
Contacts
GF 130 - Stylus UI
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