Verification with UVM for HEP Workshop

Upcoming event

Verification with UVM for HEP Workshop

February 27th to March 1st 2024

On-site at CERN

Registrations are full. You can join the waiting list in case a spot becomes free.

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Workshop description

4-day UVM verification introduction and HEP-specific topics.

Expand the full Workshop program

• Days 1-3 - SystemVerilog accelerated verification using UVM

  • Introduction to UVM Methodology
  • Data Modeling
  • Simulation Phases
  • Test and Testbench Classes
  • Creating an Interface UVC
  • Configuration
  • Type Overrides and the Factory
  • Sequences
  • Connecting to a DUT
  • Multiple UVCs
  • Multichannel (Virtual) Sequencers
  • Building a Scoreboard
  • Transaction Level Modelling (TLM)
  • Register Modelling in UVM

• Day 4 - Verification best practices for HEP

  • Verification lifecycle
  • CHIPS Verification IPs (VIP)
  • Simulations and regressions
  • Fundamentals of SEE verification
  • Introduction to the see_uvc VIP
  • SEE simulations and fault campaigns