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Verification with UVM for HEP Workshop

Upcoming event

  6th Verification with UVM for HEP Workshop

  15 - 18 September 2026

  CERN Training Center

  800 CHF/EUR

Registrations are open

Go to the event page   Register here

Disclaimer

Training workshops are offered exclusively to researchers and engineers working in the domain of microelectronics for High-Energy Physics at CERN or in collaborating institutes, including:

  • CERN MPE (staff, graduates, fellows)
  • CERN MPA (students, trainees, Users, COAS, Project Associates, etc.)
  • Employees of external institutes, provided they are part of a collaboration with CERN experiments or related HEP experiments

Additional requirements may apply for technology-specific workshops. The organizers reserve the right to request supporting documentation and may decline registrations that do not meet eligibility criteria.

Workshop description

4-day UVM verification introduction and HEP-specific topics.

Workshop program

  • MODULE 1 (Days 1 to 3) - SystemVerilog accelerated verification using UVM - Cadence

    • Introduction to UVM Methodology
    • Data Modelling
    • UVM Simulation Phases
    • Test and Testbench Classes
    • Creating an Interface UVC
    • Configuration
    • Type Overrides and the Factory
    • Sequences
    • Connecting to a DUT
    • Multiple UVCs
    • Multichannel (Virtual) Sequencers
    • Building a Scoreboard
    • Transaction Level Modelling (TLM)
    • Register Modelling in UVM

  • MODULE 2 (Day 4) - Verification best practices for HEP - CERN CHIPS Service

    • Verification lifecycle
    • CHIPS Verification IPs (VIP)
    • Simulations and regressions
    • Fundamentals of SEE verification
    • Introduction to the see_uvc VIP
    • SEE simulations and fault campaigns

Past events