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Flow-scripts library changelog

The flow-scripts library is used as submodule by all the mantained digital implementation flows based on Cadence Stylus Common-UI with flowkit.

[v2025.03]

Contributors:

Description:

  • Renames the corners and analysis views to comply with the conventions used by TSMC
  • fix SI netlisting script
  • Move CI to common repo
  • Update features definition and other improvements
  • Flow compatible with both v22.xx and v23.xx

Merge-requests:

[v2025.02]

Contributors:

Description:

  • Issue 95
    • Update Cadence flowtool base scripts to DDI v23.XX
    • Flow compatible with both v22.xx and v23.xx
  • Issue 51:
    • Fix codespell errors for passign projects linting checks
    • Update flow steps names for consistency
    • Changes for linting
  • Issue 94
    • Update naming conventions for complex ports, data structs and generate modules to simplify SEE injection
  • Issue 92
    • support for LDB compiled libraries and for tmp in local disk
  • Issue 51
    • Fix codespell errors for passign projects linting checks
    • Update flow steps names for consistency
    • Changes for linting.
  • Issue 93
    • fix minor bug for TMAKE flow in remove_std_cells_lib.

Merge-requests:

[v2025.01]

Contributors:

Description:

  • Issue 86
    • removed features control for report_defer and sta_glitch
  • Issue 87
    • Create subflow to avoid polluting flow.yaml file with schedules, report_inline and report_none features
    • Currently the flow was not clear with mix of enabled and scheduled subflows. In this case the complexity is handled behind.
  • Issue 88
    • Created standalone signoff_checks flow
    • Before signoff was scheduled from design finishing. Now a standalon flow schedle in parallel all the signoff checks:
Parallel execution order:
                                        ____Signoff STA (tempus)
             _____ Extract (Quantus)___/___ IR static (voltus)
signoff ____/_____ DRC (Calibre)       \___ IR dynamic (voltus)
  • Issue 89
    • created scheduling sub-flows for: report_synth, report_place, report_postcts, report_postroute

  • Reorganization of files

  • Issue 36

    • Report_lint missing in synthesis
  • Issue 47
    • Increase max_net_name_length in the ihdl generated script to avoid problem when generating schematic
  • Issue 41
    • Remove -turbo_all option from Calibre command
  • Issue 75
    • Generalise procedure for handling libraries into common repo

  • Created common_procedure.tcl file

  • Issue 69

    • Allow multiple signoff schedules run in parallel making copy of QRC command file
  • Issue 70
    • Update timing reports in a more coherent structure and naming across the flow
  • Issue 71
    • Added assemble design subflow and steps for flat signoff STA
  • Issue 72
    • Moove SDF export to signoff STA in tempus
  • Issue 73
    • Remoove tmr distance for tie-low and tie-high cells. It is not needed

  • Issue 74

    • Handle creating missing paths to avoid errors when running flow not linearly

  • Issue 61

    • Update TMR dont_touch constraints
  • Issue 62
    • update tmr_set_place_distance procedures
  • Issue 63
    • Update TMR voters reporting
  • Issue 64
    • Add step check_voter_connections
    • Check from @mandorno to check the registers that goes to a voter, only goes to a voter.
    • It creates a report to be evaluated by the user, according the design specific approach.
  • Issue 65
    • Fixes in postroute_advanced_opt step
    • this step was previously not usable
    • the step is disabled by default but it can now be enabled
  • Issue 66
    • Improve eco_drc_fix step
    • The eco_route -fix_drc had limited capabilities.
  • Issue 67
    • Improve TMR voters checks
    • Check that the voter instances are not removed while proceeding in different design phases
    • It creates a report to be evaluated by the user, according the design specific approach.
  • Issue 68
    • Improve TMR distance checks including clock source origin in reporting
    • The check was reporting instances according regex on the name conventions. Now it does in addition based on the source of the clock tree.
    • It creates a report to be evaluated by the user, according the design specific approach.
  • Issue 84
    • List triplicated and non-triplicated latches in addition to flip-flops
    • Follow-up from !21 @pevicent suggestion
  • Issue 85
    • Remove base cell names dependencies in scripts
    • Follow-up from !21 @pevicent suggestion
  • Issue 83
    • Generalize power layers names for technology independence
    • Follow-up from !21 @pevicent suggestion
  • Changes for linting.

Merge-requests:

[v2024.12]

Contributors:

Description:

  • Issue 60
    • Update non-default routing rules for CTS
  • Issue 58
    • Set cts_update_clock_latency to false for top-level implementation.
    • If not explicitly specified (with the command set_db cts_update_clock_latency false), Innovus CTS engine applies by default the concept of “Source Latency Update”, calculating and employing updated SDC constraints for clock pin latencies. Those latencies are derived according to the results obtained during the clock tree synthesis step (in particular the achieved insertion delay) and are necessary to ensure that “after CTS, when clocks are switched to propagated mode, I/O timing and inter-clock timing is consistent with the ideal mode timing model”. In a top-level flow, this setting should be off. For a block level design, is up to the designer.
  • Issue 59
    • Convert clock tree latencies from liberty file for hierarchical design.
    • The concept of Clock latency update takes into account the achieved clock insertion delay inside the block. If you don’t use the ILM model suggested by Cadence Support, one way to provide information about the clock tree depth inside a hierarchical module to the top level CTS engine is to use the command convert_lib_clock_tree_latencies, which instructs the top level of the design about the clock tree path contained inside you macro block.
  • Issue 82
    • Generalize CTS steps to be independent on the technology layers naming convention. Follow-up from !19 comments
  • added init_innovus_preconfig for messages settings
  • Issue 55
    • Fix elif {[is_flow -inside ..]} bug was preventing settings to be applied when needed.
  • Issue 56
    • Update Innovus set_db attributes
  • Issue 57
    • Suppress errors on TSMC libraries replicated instances
  • Issue 58
    • Set cts_update_clock_latency to false for top-level implementation.
    • If not explicitly specified (with the command set_db cts_update_clock_latency false), Innovus CTS engine applies by default the concept of “Source Latency Update”, calculating and employing updated SDC constraints for clock pin latencies.
  • Issue 52
    • update tempus setting for signoff STA
  • Issue 53
    • Add OCV derate settings in Tempus signoff STA
  • Issue 54
    • Add OCV settings in multiple steps since it is not mantained reloading the database
  • Minimal reorganization of the code porting the flow.yaml and the innovus config inside the common-scripts repository (#50)
  • Fix some codespell errors (#51)
  • Reassign step owner to cern for custom steps
  • A bit of cleaning

Merge-requests:

[v2024.04]

Contributors:

Merge-requests:

Description:

  • Issue 42
    • the common scripts were not (yet) tech agnostic as there was a SDF* in the scan chain declaration, therefore set the scan chain naming as a config
  • Issue 43
    • There was no step to write the netlist at the synthesis stage
  • Issue 44
    • The way the physical cells were defined was not yet tech agnostic only apply set_dont_use if scan chain cell exists
  • Added CI tests
  • Updated for 2024 tool releases
  • Bug fixes

[v2023.12]

Contributors:

Description:

  • Refactored repository for Tmake integration
  • multiple changes in structures
  • impruved support for multiple technologies
  • Multiple issues closed
  • most of changes are in the common-scripts repository

[v2023.03]

Contributors:

Description:

  • Reorganized the structure of flow repositories using submodules
  • Moved flow on 2023 Europractice releases

[v2023.01]

Contributors:

Description:

  • Added Calibre DRC and LVS steps
  • Added custom message suppression
  • Modified cds.lib creation step
  • Bug fixes
  • Added Gitlab CI for release generation
  • Added config directory variables in setup.yaml
  • Added Voltus XY file support to setup.yaml
  • Moved signoff flow to design finishing
  • Moved out export and physical verification flows
  • Bug fixes

[v2022.11]

Contributors:

Description:

  • Bug fixes
  • Fixed missing flow for TMR feature
  • Fixed bug when using multiple libraries in the MMMC
  • Fixed README
  • Removed old Stylus flow and scripts. Flowkit is now the main flow.

[v2022.05]

Contributors:

Description:

  • Initial release

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