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Innovus optimization instance naming reference

This guide provides a reference for instance names of buffer cells and nets added by Innovus during place and route optimization stages.

Timing optimization

Instance/net name Description Origin
FE_MDBC Instance added by multi-driver net buffering optDesign
FE_MDBN Net added by multi-driver net buffering optDesign
FE_OCP_RBC Instance added by rebuffering optDesign
FE_OCP_RBN Net added by rebuffering optDesign
FE_OCPC Instance added by critical path optimization optDesign
FE_OCPN Net added by critical path optimization optDesign
FE_OFC Buffer instance added by rule-based buffer insertion or DRV fixing insertRepeater/optDesign
FE_OFN Buffer net added by rule-based buffer insertion or DRV fixing insertRepeater/optDesign
FE_PHC Instance added by hold time repair optDesign
FE_PHN Net added by hold time repair optDesign
FE_PSBC Instance added by buffer insertion in optDesign postRoute optDesign
FE_PSBN Net added by buffer insertion in optDesign postRoute optDesign
FE_PSC Instance added by postroute setup repair optDesign
FE_PSN Net added by postroute setup repair optDesign
FE_PSRN Net added by postRoute restructuring optDesign
FE_RC Instance created by netlist restructuring optDesign
FE_RN Net created by netlist restructuring optDesign
FE_USC Instance added during useful skew optimization optDesign
FE_PDC Instance added by postroute DRV fixing optDesign
FE_PDN Net added by postroute DRV fixing optDesign
FE_RAC Instance added by reclaim optimizer optDesign
FE_RAN Net added by reclaim optimizer optDesign

Feedthrough buffers for partitions

Instance/net name Description Origin
FE_FEEDX_BUF FeedThrough Buffers addBufferForFeedthrough/insertPtnFeedthrough
FE_FEEDX_NET FeedThrough nets addBufferForFeedthrough/insertPtnFeedthrough
FE_FEEDX_NET_C Used for normal FeedThrough nets addBufferForFeedthrough/insertPtnFeedthrough
FE_FEEDX_NET_D Used for FeedThrough nets, when a new driver is made. If this does not exist, the original net is still the driver net. addBufferForFeedthrough/insertPtnFeedthrough
FE_FEEDX_NET_I Used for FeedThrough nets connecting buffers within a partition if -doubleBuffer is used addBufferForFeedthrough/insertPtnFeedthrough
FE_FTN_n Net Names where n is an integer addBufferForFeedthrough/insertPtnFeedthrough
FE_FTB_n Buffer Names where n is an integer addBufferForFeedthrough/insertPtnFeedthrough
FE_DBTC* Used during inverter decloning in deleteBufferTree stage addBufferForFeedthrough/insertPtnFeedthrough
FE_FTM_x_netName Nets that connect to FeedThrough output pins addBufferForFeedthrough/insertPtnFeedthrough

Assign statement buffers

Instance name Description Origin
buf_dummy__# Buffer names added to remove assign statements optDesign

Spare cells

Instance name Description Origin
FE_spare Default prefix for instances added by addSpareInstance. Use the -prefix option to override this. addSpareInstance
spr_gate# Instance name of spare cells where # is an integer placeSpareModule
_SPARE Default suffix for instances converted to spare cells. Use the -suffix option to override this. ecoDesign/ecoDefIn

Interactive ECO cells

Instance/net name Description Origin
FEC# An instance added by interactive ECO. Default prefix is ECO. Override prefix with setEcoMode -prefixName. ecoAddRepeater
FEN# A net added by interactive ECO. Default prefix is ECO. Override prefix with setEcoMode -prefixName. ecoAddRepeater

FE-CTS (clockDesign, ckSynthesis, ckECO)

Instance/net name Description Origin
__Lx_Ix Name of instances added by CTS. clk is the AutoCTS root clock name. L is the depth/level. I is the instance count in that level where x is an integer. clockDesign/ckSynthesis
__Lx_Nx Name of nets added by CTS. N is the net name. clockDesign/ckSynthesis
FECTS_CLONE_I# Cloned instances ckCloneGate
FECTS_CLONE_N#clk__Lx_Nx Nets created when cloning instances ckCloneGate

Example

In the following example, clk0 is the clock name, L6 is on level 6, and I2 is the second instance under that level: 

clk0__L6_I2/A       345.5 288.1 300(ps)
clk0__L7_I4/A       346.2 296.3 300(ps)
clk0__L9_I11/A      351.6 299.9 300(ps)
clk0__L9_I10/A      361.5 305.9 300(ps)

Antenna diode

Instance name Description Origin
antenna Antenna diode cells routeDesign/globalDetailRoute/ecoRoute

Physical cells

Instance name Description Origin
FILLER_impl#_# Default prefix for filler cells. Override with setFillerMode -corePrefix or addFiller -prefix. impl# indicates implant layer, and _# is a unique integer. addFiller
WELLTAP Default prefix for well tap cells. Override with the -prefix option. addWellTap
ENDCAP Default prefix for endcap cells. Override with -prefix option. addEndCap

Tie HI/LO cells

Instance name Description Origin
L# L is empty string “” by default. Use the -prefix option to specify prefix. Added cells have the name L# where # is a unique integer. setAddTieHiLoMode/addTieHiLo

CTS internal stages

CCopt instance naming convention

CTS_ccl_BUF_my_clk_G1_L4_1
    A   B   C      D  E  F
  • A: CCOpt’s internal stage (see table below)
  • B: Cell type (BUF or INV)
  • C: Clock tree name
  • D: Level of clock gating cells (G0, G1, G2, ...)
  • E: Level of logic gates (L1, L2, ...)
  • F: Number of cells with same levels (1, 2, ...)
Stage name Description
CTSG Unnamed - this should not be used any more.
cuk Cts: Unknown creator, will not appear in the netlist.
ccl_a Cts: Created during clustering by the agglom clustering algorithm.
cbi Cts: Created by the swapping buffers and inverters for power.
cex Cts: Existing cells in the clock tree which cannot be removed.
coi Cts: Cells created as a result of cancelling out inversions
lbl Cts: Created by the clustering process to meet the slew target
ccl Cts: Created by the clustering process to meet the slew target
ccd Cts: Created by clustering for balancing the tree - these cells are not necessary to meet the slew target.
cci Cts: Created by the clustering process to fix inversion.
csf Cts: Created by the CTS slew fixing step in cases where clustering did not meet the slew target.
cms Cts: Created during the process of physically moving clock gates to improve their enable timing.
cid Cts: Created by CTS on the outputs of weak driving cells to reduce insertion delay.
cdb Cts: Created by CTS to balance the delays in the clock tree.
cwb Cts: Created by CTS to balance the wire delays in the clock tree.
cfo Cts: Created by CTS to reduce fanout skew.
csk Cts: Created by the CTS skew fixing step to finely balance the clock tree.
cmf Cts: Created by CTS to buffer long nets.
cbc Cts: Created by the clock tree conditioning step to clone off sub trees that cannot optimized by gated synthesis, such as those parts above RAMs, black boxes, and lockup latches.
css Cts: Created by the early cloning of simple sink allocations.
cdc Cts: A clock driver created by adding driver cell process for attribute cts_add_driver_cell.
cpd Cts: A clock driver created below an input port or above an output port specified by attribute cts_add_port_driver.
ccg Cts: A clock gate created by one of the gated synthesis algorithms.
cse Cts: A clock driver created above exclude pins to remove them from the clock tree.
cfh Cts: A clock driver created as part of a flexible H-tree.
cat Cts: Created by the insert_ccopt_source_group_roots command
cpc_drv Cts: A clock driver created by post conditioning.
cpc_sk Cts: A clock driver created by post conditioning.
PRO Post-route optimization.
PRO_drv Post-route optimization.
PRO_sk Post-route optimization.
sfc Cloned by slew fixing.
ccc Cts: Created by the clone_clock_cells command.
grb Cts: A clock driver created by global route buffering.
sgb Cts: A clock driver created by source group balancing.
idc Cloned to reduce insertion delay
vgb Cts: A clock driver created by VG buffering.
USK skewClock