Integration of non-OA IP blocks into a Digital-on-Top design flow
Many foundry IP blocks, namely SRAM and register file macros, do not come with an Cadence OpenAccess library out of the box. In order to integrate them into the CERN ASIC Support Digital-on-Top implementation flow, there are a few steps to be taken, in particular:
- Create an OA library
- Add the relevant files in the flow configuration